1. Field of the Invention
The present invention relates to a semiconductor read only memory, and more particularly to a semiconductor read only memory in which MOSFETs constituting memory cells are connected in parallel.
2. Description of the Related Art
FIG. 4 shows an equivalent circuit of a semiconductor read only memory (hereinafter, sometimes referred to simply as "a ROM") which is conventionally and widely used. This ROM is a lateral ROM constructed in such a manner that memory cells 3 of MOSFETs are connected in parallel with respect to a plurality of bit lines 2 which cross word lines 1. Conventionally, each of the bit lines 2 is made of metal (hereinafter, referred to as a metal bit line). Alternatively, a diffused layer may function as a bit line (hereinafter, referred to as a diffusion bit line).
In order to dispose memory cells more densely, a hierarchical system (hereinafter, referred to as a hierarchical bit line system) has been proposed (Japanese Patent Application No. 63-75300), as is shown in FIG. 5. In the system, main bit lines Mb.sub.l, Mb.sub.l+1, . . . , etc. and sub-bit lines Sbm.sub.2l, Sbm.sub.2l+1, . . . , etc. are hierarchically provided In the hierarchical bit line system, each of the memory cells Mm.sub.21.n is connected between two adjacent sub-bit lines Sbm.sub.21 and Sbm.sub.2l-1. The plurality of memory cells Mm.sub.2l.k (1.ltoreq.k.ltoreq.n) of each row are connected to a common word line WL.sub.k. The memory cells Mm.sub.21.n are alternately assigned into two groups of odd-numbered banks such as Bm.sub.2l-1 and even-numbered banks such as Bm.sub.2l. For the selection of these banks, bank select MOSFETs Q0.sub.m.21, QE.sub.m.2l, . . . , etc. are provided on both ends of the sub-bit lines, respectively. Bank select lines B0.sub.m and BE.sub.m are connected to these bank select MOSFETs, respectively. The main bit lines Mb.sub.l, Mb.sub.l+1, . . . , etc. are connected to sense amplifiers such as SA.sub.l, or connected to GND via MOSFETs such as Q.sub.l+1.
In the ROM with the hierarchical bit line system, the wired pitch of the main bit lines can be made double as compared with the conventional lateral ROM shown in FIG. 4. The ROM with the hierarchical bit line system can advantageously reduce the parasitic capacitance on bit lines, and especially when the diffusion bit lines are used, the wiring resistance on bit lines can be greatly reduced
However, when the diffusion bit lines are used in the hierarchical bit line system shown in FIG. 5, there arises a problem in that the diffusion resistance greatly varies depending on the position of a memory cell in a bank, which is described below, so that the value of discharge current for the read of information greatly varies depending on the position of the memory cell.
There is another problem in that since the value of the diffusion resistance is large and hence the value of the discharge current is small, such a ROM is not suitable for a high-speed read operation.
For example, a case where information is read out from a memory cell Mm.sub.2l-1.1 by setting the bank select line B0.sub.m High, the other bank select line BE.sub.m Low, and the word line WL.sub.1 High is considered. In this case, a control signal VG for a transistor Q.sub.1 (not shown) connected to the main bit line Mb.sub.l is made Low. A control signal VG for a transistor Q.sub.l-1 connected to the adjacent main bit line Mb.sub.l-1 is made High. As a result, the main bit line Mb.sub.l-1 is connected to the GND. The circuit in the above-mentioned state is shown in FIG. 6. A discharge current i flows through a path formed by the main bit line Mb.sub.l, the bank select MOSFET Q0.sub.m.2l-1, the sub-bit line Sb.sub.m2l-1 the memory cell Mm.sub.2l-1.1, the sub-bit line Sb.sub.m2l-2, a bank select MOSFET Q0.sub.m.2l-2, and the main bit line Mb.sub.l-1, in this order. The total value of diffusion resistance of the sub-bit lines Sbm.sub.2l-1 and Sbm.sub.21-2 in this path is 2r, where r indicates the diffusion resistance between respective two memory cells. The total diffusion resistance value varies depending on the position of the selected memory cell, and the possible largest value of the total diffusion resistance is 2nr.
As described above, in the ROM shown in FIG. 5, the value of diffusion resistance greatly varies depending on the position of a memory cell from which information is read out. Moreover, the discharge current flows through three transistors, so that the ROM shown in FIG. 5 has a poor discharge ability as compared with a system without bank select MOSFETs (in such a system, the discharge current flows through only one transistor).